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MC100E210 5V ECL Dual 1:4, 1:5 Differential Fanout Buffer
The MC100E210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part-to-part skew down to an output-to-output skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111's to accomplish the same task. The lowest TPD delay time results from terminating only one output pair, and the greatest TPD delay time results from terminating all the output pairs. This shift is about 10-20 pS in TPD. The skew between any two output pairs within a device is typically about 25 nS. If other output pairs are not terminated, the lowest TPD delay time results from both output pairs and the skew is typically 25 nS. When all outputs are terminated, the greatest TPD (delay time) occurs and all outputs display about the same 10-20 pS increase in TPD, so the relative skew between any two output pairs remains about 25 nS. For more information on using PECL, designers should refer to Application Note AN1406/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. * Dual Differential Fanout Buffers * 200 ps Part-to-Part Skew * 50 ps Typical Output-to-Output Skew * Low Voltage ECL/PECL Compatible * The 100 Series Contains Temperature Compensation * 28-lead PLCC Packaging * PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V * NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V * Internal Input 75 KW Pulldown Resistors * Q Output will Default LOW with Inputs Open or at VEE * ESD Protection: Human Body Model; >2 KV, Machine Model; >200 V * Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test * Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D * Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index: 28 to 34 * Transistor Count = 179 devices
http://onsemi.com MARKING DIAGRAM
1 28
MC100E210FN AWLYYWW PLCC-28 FN SUFFIX CASE 776
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC100E210FN MC100E210FNR2 Package PLCC-28 Shipping 37 Units / Rail
PLCC-28 500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2003
1
October, 2003 - Rev. 2
Publication Order Number: MC100E210/D
MC100E210
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Qa0 Qa0 Qa1 VCCO Qa1 Qa2 Qa2 25 VEE VBB CLKa VCC CLKa CLKb CLKb 26 27 28 1 2 3 4 5 6 7 8 9 10 11 Qb0 Qb0 CLKb CLKb Qb1 Qb1 Qb2 Qb2 Qb3 Qb3 Qb4 Qb4 VBB 24 23 22 21 20 19 18 17 16 Qa3 Qa3 Qb0 CLKa 15 14 13 12 VCCO Qb0 Qb1 Qa3 Qb1 Qa3 CLKa
LOGIC SYMBOL
Qa0 Qa0 Qa1 Qa1 Qa2 Qa2
28-Lead PLCC (Top View)
Qb4 Qb4 Qb3 VCCO Qb3 Qb2 Qb2 Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
PIN DESCRIPTION
PIN CLKa, CLKb CLKa, CLKb Qa0:3, Qb0:4 Qa0:3, Qb0:4 VBB VCC, VCCO VEE FUNCTION ECL Differential Input Pairs ECL Differential Input Pairs ECL Differential Outputs ECL Differential Outputs Reference Output Voltage Positive Supply Negative Supply
MAXIMUM RATINGS (Note 1)
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC VEE Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) PECL Operating Range NECL Operating Range Wave Solder <2 to 3 sec @ 248C 0 LFPM 500 LFPM Standard Board 28 PLCC 28 PLCC 28 PLCC Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 -8 6 -6 50 100 0.5 0 to +85 -65 to +150 63.5 43.5 22 to 26 4.2 to 5.7 -5.7 to -4.2 265 Unit V V V V mA mA mA C C C/W C/W C/W V V C
1. Maximum Ratings are those values beyond which device damage may occur.
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PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL NOTE: Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 4) Input HIGH Current Input LOW Current 0.5 0.3 3915 3170 3835 3190 3.62 2.7 3995 3305 3975 3355 Min Typ Max 55 4120 3445 4120 3525 3.74 4.6 150 0.5 0.25 3975 3190 3835 3190 3.62 2.7 4050 3255 3975 3355 Min 25C Typ Max 55 4120 3380 4120 3525 3.74 4.6 150 0.5 0.2 3975 3190 3835 3190 3.62 2.7 4050 3260 3975 3355 Min 85C Typ Max 65 4120 3380 4120 3525 3.74 4.6 150 Unit mA mV mV mV mV V V mA mA
Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 2. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 3. Outputs are terminated through a 50 W resistor to VCC - 2 volts. 4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= -5.0 V (Note 5)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL NOTE: Characteristic Power Supply Current Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) Input HIGH Current Input LOW Current 0.5 0.3 -1085 -1830 -1165 -1810 -1.38 -2.3 -1005 -1695 -1025 -1645 Min Typ Max 55 -880 -1555 -880 -1475 -1.26 -0.4 150 0.5 0.25 -1025 -1810 -1165 -1810 -1.38 -2.3 -950 -1745 -1025 -1645 Min 25C Typ Max 55 -880 -1620 -880 -1475 -1.26 -0.4 150 0.5 0.2 -1025 -1810 -1165 -1810 -1.38 -2.3 -950 -1740 -1025 -1645 Min 85C Typ Max 65 -880 -1620 -880 -1475 -1.26 -0.4 150 Unit mA mV mV mV mV V V mA mA
Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 5. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 6. Outputs are terminated through a 50 W resistor to VCC - 2 volts. 7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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MC100E210
AC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= -5.0 V (Note 8)
-40C Symbol fMAX tPLH tPHL tskew Characteristic Maximum Toggle Frequency Propagation Delay to Output IN (differential) (Note 9) IN (single-ended) (Note 10) Within-Device Skew Qa to Qb Qa to Qa,Qb to Qb Part-to-Part Skew (Differential) (Note 11) Random Clock Jitter (RMS) Input Voltage Swing (Differential Configuration) (Note 12) Output Rise/Fall Time (20%-80%) 500 200 600 475 400 50 50 <1 500 200 600 Min Typ 700 675 700 75 75 200 500 450 50 30 <1 500 200 600 Max Min 25C Typ 700 700 750 75 50 200 500 450 50 30 <1 Max Min 85C Typ 700 700 750 75 50 200 ps Max Unit MHz ps
tJITTER VPP tr / tf
ps mV ps
8. VEE can vary -0.46 V / +0.8 V. 9. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 10. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 11. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 12. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the E210 as a differential input as low as 50 mV will still produce full ECL levels at the output.
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MC100E210
Q Driver Device Q 50 W 50 W
D Receiver Device D
V TT VTT = VCC - 2.0 V
Figure 1. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020 - - - - - - - - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE Modeling Kit Metastability and the ECLinPS Family Interfacing Between LVDS and ECL ECLinPS Lite Translator ELT Family SPICE I/O Model Kit Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes Termination of ECL Logic Devices
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MC100E210
PACKAGE DIMENSIONS
PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E
B -NY BRK U
0.007 (0.180)
M
T L -M
M
S
N
S S
0.007 (0.180)
T L -M
N
S
D Z -L-M-
W
V
D X VIEW D-D G1
0.010 (0.250)
S
T L -M
S
N
S
28
1
A
0.007 (0.180)
M M
T L -M T L -M
S S
N N
S S
H
0.007 (0.180)
M
Z
T L -M
S
N
S
R
0.007 (0.180)
C
E
0.004 (0.100)
K1
G G1
0.010 (0.250)
J
-T-
SEATING PLANE
K F VIEW S
0.007 (0.180)
VIEW S
M
T L -M
S
N
S
S
T L -M
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 0.020 10 2 0.410 0.430 0.040
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.57 4.20 2.79 2.29 0.48 0.33 1.27 BSC 0.81 0.66 0.51 0.64 11.58 11.43 11.58 11.43 1.21 1.07 1.21 1.07 1.42 1.07 0.50 10 2 10.42 10.92 1.02
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MC100E210
Notes
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MC100E210
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC100E210/D

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